Processors incorporated in portable information terminals are expected to consume low power. In order to reduce the power of processors, a method is suggested, in which an SRAM (Static Random Access Memory)-based cache memory that consumes a large standby power is replaced with an SRAM including non-volatile elements. As the transistors in SRAMs are downsized, leakage power increases in both the operating mode and the standby mode. If a cache memory is replaced with a non-volatile SRAM, unnecessary power supply can be cut off. This leads to a reduction in standby power consumption.
A non-volatile SRAM that is based on SRAM cells each including, for example, six MOS transistors has been suggested as a non-volatile memory that can perform high-speed SRAM operations. For example, a non-volatile SRAM including SRAM cells each including six transistors and two magnetic tunnel Junction (MTJ) elements as magnetoresistive memory devices is suggested. Such a non-volatile SRAM has an SRAM cell configuration in which there is a leakage current path from a power supply to GND. This non-volatile SRAM can reduce standby power consumption because of its non-volatile characteristics, but cannot reduce the operating power consumption.